July, 2024 - present
Cover all DFT features for implementing DFT and debugging results.
Built-In Self Test
Memory-BIST
Logic-BIST
BoundaryScan
In-System-Test(Mission-Mode)
Scan
TestKompress(EDT)
Streaming Scan Network(SSN)
Boundary Scan
June, 2018 - July, 2024
Cover all DFT features for implementing DFT and debugging results.
Built-In Self Test
Memory-BIST
Logic-BIST
In-system-Test(Mission-Mode)
Scan
TestKompress(EDT)
Streaming Scan Network(SSN)
Boundary Scan
Provide training on Tessent DFT products.
Regular Memory-BIST training at Siemens office
On-demand training tailored to customers needs
Support Tessent product users
Samsung, SK hynix, LX Semicon, and LG
SemiFive, ADT, and etc
2017 - 2018
Full Chip on TSMC 16nm(FinFet) process with gate count of 5M
Synthesized full chip using DCG Flow with multi-bit registers
Implemented streaming compression scan architecture using DFTMAX Ultra
Sub-Module on TSMC 28nm process with gate count of 100M
Closed Sub-Module Timing Constraints
Target speed : 600Mhz
2011-2017
Full Chip on SamSung 10nm process with gate count of 32M
Led a team of engineers
Chip size : 6300um X 6300um
Implemented shared input dedicated output scan architecture using DFT-Compiler
Implemented Tessent MBIST
Closed Full Chip Timing Constraints
Target speed : 1.2Ghz
Sub-Module on SamSung 14nm process with gate count of 105M
Closed Sub-Module Timing Constraints
Target speed : 750Mhz
Full Chip on SamSung 28nm process AP with gate count of 43M
Achieved 98% Stuck-at test coverage with 12,000 patterns
Implemented fully shared IO Scan-In/Out architecture using DFT-Compiler
Closed Sub-Module Timing Constraints
Full Chip on SamSung 28nm process AP with gate count of 43M
Achieved 98% Stuck-at test coverage with 12,000 patterns
Implemented partially shared IO Scan-In/Out architecture using DFT-Compiler
Closed Sub-Module Timing Constraints